Digital Systems and Computer Networks group

group leader

prof. dr. sc. Julije Ožegović

associates

prof. dr. sc. Ivica Puljak
doc. dr. sc. Duje Čoko
dr. sc. Vesna Pekić
mag. ing. asistent, Marina Prvan

Research Topics

  1. Flow control in packet networks
  2. Quality of Service (QoS)
  3. MAC protocols in wireless networks
  4. Protocol modeling
  5. Logic design for programmable logic architectures
  6. Logic design for application specific circuits

Description of the Laboratory and equipment

Computer Networks Laboratory

  • Cisco router 1841-SEC/K9
  • Cisco switch WS-C2960-24TT-L
  • HP switch ProCurve 2626 J4900B
  • D-link firewall DFL-200
  • Planet switch WSD-800
  • Planet AP/router WRT-414
  • Planet WLAN WL-u356a

 

Digital Systems Laboratory

  • Xilinx Spartan-3e FPGA
  • Xilinx CoolRunner-ii CPLD
  • Analog Devices Blackfin BF533 DSP
  • Analog Devices Blackfin BF537 DSP
  • Tektronix digital oscilloscope
  • HP 8012 pulse generator
  • ALL-100 programmer
  • ALL-11 P2 programmer
  • ALL-03 programmer
  • DELAB1 laboratory model
  • 25 academic licenses for XILINX Vivado IDE.
  • ASIC development system Cadence (Europractice IC package)
project title

Wireless Media Access Mechanisms Modelling (MAMM)

Project research activities

Previous research in the proposed field has resulted in the development of new mathematical models of media access, development of improved algorithms and mechanisms for wireless media access, defense of five doctoral dissertations, publication of four A articles, and publication of twelve D articles. Previous research has resulted in a US patent. In 2017, the ASIC Cadence design system was installed and is in use, and in 2018 it was upgraded with CERN 65nm CMOS technology libraries. Work continued on modeling the geometry of the sensor system through doctoral research, and work continued on optimizing the system for selecting the best sample adapted to the ECAL architecture of the CMS detector through installation on the test plant. The project with FERMILAB on the design of ASIC ECON-T in the part of the tripled IIC interface was successfully completed. Through 2019/2020, simulation tests were performed, and the BC (Best Choice) module of the algorithm was successfully realized and submitted in cooperation with FERMILAB on the design of the ASIC ECON-T.

 

In the five-year period, work is planned to continue in the proposed areas, with an emphasis on building the system and further training of the Specific Integrated Circuits (ASIC) design team in line with the FESB development strategy. Special attention is paid to the development of ASIC systems for operation under high radiation. Work is underway to develop FPGA algorithms at the L1 and L2 trigger levels in collaboration with LLR Paris. It is planned to improve and upgrade the geometry model of the sensor system, and to complete the web interface for access to the architecture generator.

 

Work on the project over a five-year period should result in the publication of about five articles in Category A journals, and about five articles in international conferences and Category B journals. Several visits of team members related to current research are planned (LLR Paris, France), one stay on the preparation of a doctorate and several stays related to current research, part of which were realized in 2017 to 2019, and activities planned for 2020 were postponed due to COVID-19.